BCD=BCD_0, BCP=BCP_0, BCI=BCI_0, BCS=BCS_0, MSEL=MSEL_0, SYNC=SYNC_0
SAI Transmit Configuration 2 Register
| DIV | Bit Clock Divide |
| BCD | Bit Clock Direction 0 (BCD_0): Bit clock is generated externally in Slave mode. 1 (BCD_1): Bit clock is generated internally in Master mode. |
| BCP | Bit Clock Polarity 0 (BCP_0): Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 (BCP_1): Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. |
| MSEL | MCLK Select 0 (MSEL_0): Bus Clock selected. 1 (MSEL_1): Master Clock (MCLK) 1 option selected. 2 (MSEL_2): Master Clock (MCLK) 2 option selected. 3 (MSEL_3): Master Clock (MCLK) 3 option selected. |
| BCI | Bit Clock Input 0 (BCI_0): No effect. 1 (BCI_1): Internal logic is clocked as if bit clock was externally generated. |
| BCS | Bit Clock Swap 0 (BCS_0): Use the normal bit clock source. 1 (BCS_1): Swap the bit clock source. |
| SYNC | Synchronous Mode 0 (SYNC_0): Asynchronous mode. 1 (SYNC_1): Synchronous with receiver. |